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Disambiguation of "Tsai, Chien-Chung"

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Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.

, , , , , , , and . ITC, page 74-82. IEEE Computer Society, (2002)

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Phi-Long Chung University of Stuttgart

 

Other publications of authors with the same name

Synthesis of Scan Chains for Netlist Descriptions at RT-Level., , , , , and . J. Electronic Testing, 18 (2): 189-201 (2002)Boolean Functions Classification via Fixed Polarity Reed-Muller Forms., and . IEEE Trans. Computers, 46 (2): 173-186 (1997)Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms., and . ISCAS, page 287-290. IEEE, (1994)Generalized Reed-Muller Forms as a Tool to Detect Symmetries., and . IEEE Trans. Computers, 45 (1): 33-40 (1996)Multilevel Logic Synthesis for Arithmetic Functions., and . DAC, page 242-247. ACM Press, (1996)Efficient minimization algorithms for fixed polarity AND/XOR canonical networks., and . Great Lakes Symposium on VLSI, page 76-79. IEEE, (1993)Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets., , , , and . ISQED, page 99-104. IEEE Computer Society, (2003)Constraint Driven Pin Mapping for Concurrent SOC Testing., , , , , , , and . VLSI Design, page 511-516. IEEE Computer Society, (2002)A novel combinational testability analysis by considering signal correlation., , , and . ITC, page 658-667. IEEE Computer Society, (1998)On Concurrent Test of Core-Based SOC Design., , , , , , and . J. Electronic Testing, 18 (4-5): 401-414 (2002)