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A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.

T. Tahmoureszadeh, S. Sarvari, A. Sheikholeslami, H. Tamura, Y. Tomita, and M. Kibune. CICC, page 1-4. IEEE, (2010)

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A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.N. Nedovic, A. Kristensson, S. Parikh, S. Reddy, S. McLeod, N. Tzartzanis, K. Kanda, T. Yamamoto, S. Matsubara, M. Kibune and 13 other author(s). J. Solid-State Circuits, 45 (10): 2016-2029 (2010)Speed-Up of Object Detection Neural Network with GPU.T. Fukagai, K. Maeda, S. Tanabe, K. Shirahata, Y. Tomita, A. Ike, and A. Nakagawa. ICIP, page 301-305. IEEE, (2018)What is a good way to expand a silicon value to a solution value?T. Chiueh, T. Shimizu, G. Chen, C. Lee, C. Hsu, T. Chiang, Z. Wang, J. Choi, J. Lee, Y. Tomita and 1 other author(s). A-SSCC, page 389-394. IEEE, (2014)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa and 2 other author(s). IEICE Transactions, 93-C (3): 295-302 (2010)An Automated CNN Recommendation System for Image Classification Tasks.S. Wang, L. Sun, W. Fan, J. Sun, S. Naoi, K. Shirahata, T. Fukagai, Y. Tomita, and A. Ike. CoRR, (2016)GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning.K. Shirahata, Y. Coppens, T. Fukagai, Y. Tomita, and A. Ike. IJNC, 8 (2): 408-433 (2018)An FPGA-accelerated partial duplicate image retrieval engine for a document search system.H. Matsumura, M. Sugimura, H. Yamasaki, Y. Tomita, T. Baba, and Y. Watanabe. WACV, page 1-7. IEEE Computer Society, (2016)An FPGA-accelerated partial image matching engine for massive media data searching systems.T. Shimizu, Y. Tomita, H. Matsumura, M. Sugimura, H. Yamasaki, D. Thach, T. Miyoshi, T. Baba, Y. Watanabe, and A. Ike. VLSI Circuits, page 1-2. IEEE, (2016)A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.O. Tyshchenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, and T. Yamamoto. ISSCC, page 166-167. IEEE, (2010)A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.T. Tahmoureszadeh, S. Sarvari, A. Sheikholeslami, H. Tamura, Y. Tomita, and M. Kibune. CICC, page 1-4. IEEE, (2010)

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A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.

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A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers.