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2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.

H. Sayadi, H. Makrani, S. Dinakarrao, T. Mohsenin, A. Sasan, S. Rafatirad, and H. Homayoun. DATE, page 728-733. IEEE, (2019)

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Wide I/O or LPDDR? Exploration and analysis of performance, power and temperature trade-offs of emerging DRAM technologies in embedded MPSoCs.M. Hajkazemi, M. Tavana, and H. Homayoun. ICCD, page 62-69. IEEE Computer Society, (2015)A centralized cache miss driven technique to improve processor power dissipation.H. Homayoun, M. Makhzan, J. Gaudiot, and A. Veidenbaum. ICSAMOS, page 195-202. IEEE, (2008)Hot peripheral thermal management to mitigate cache temperature variation.H. Homayoun, M. Rahmatian, V. Kontorinis, S. Golshan, and D. Tullsen. ISQED, page 755-763. IEEE, (2012)A 64-core platform for biomedical signal processing.J. Bisasky, H. Homayoun, F. Yazdani, and T. Mohsenin. ISQED, page 368-372. IEEE, (2013)Temperature aware thread migration in 3D architecture with stacked DRAM.D. Zhao, H. Homayoun, and A. Veidenbaum. ISQED, page 80-87. IEEE, (2013)Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering.T. Winograd, G. Shenoy, H. Salmani, H. Mahmoodi, S. Rafatirad, and H. Homayoun. ACM Trans. Design Autom. Electr. Syst., 23 (6): 76:1-76:21 (2018)Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.A. Sasan, K. Amiri, H. Homayoun, A. Eltawil, and F. Kurdahi. IEEE Trans. VLSI Syst., 20 (4): 630-642 (2012)Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations.M. Malik, A. Sasan, R. Joshi, S. Rafatirah, and H. Homayoun. ISPASS, page 153-154. IEEE Computer Society, (2016)Co-clustering of diseases, genes, and drugs for identification of their related gene modules.A. Koohi, H. Homayoun, J. Xu, and M. Orooji. ICACI, page 407-411. IEEE, (2016)IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure.A. Vakil, H. Homayoun, and A. Sasan. ASP-DAC, page 152-159. ACM, (2019)

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2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.

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2SMaRT: A Two-Stage Machine Learning-Based Approach for Run-Time Specialized Hardware-Assisted Malware Detection.