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A centralized cache miss driven technique to improve processor power dissipation.

, , , and . ICSAMOS, page 195-202. IEEE, (2008)

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Alexander Verl

On the Dynamics and Emergency Stop Behavior of Cable-Driven Parallel Robots, , and . ROMANSY 21 - Robot Design, Dynamics and Control, volume 569 of CISM International Centre for Mechanical Sciences, page 431--438. Switzerland, Springer Verlag and Springer International Publishing, (2016)

Dr. rer. nat. Alexander Schlaich University of Stuttgart

Supporting Information: Chemical Potential Differences in Nanoscopic Teflon/Kapton Capillaries, and . Software, (2024)Related to: Artemov, V.; Frank, L.; Doronin, R.; Stärk, P.; Schlaich, A.; Andreev, A.; Leisner, T.; Radenovic, A.; Kiselev, A. The Three-Phase Contact Potential Difference Modulates the Water Surface Charge. J. Phys. Chem. Lett. 2023, 14, 4796-4802. doi: 10.1021/acs.jpclett.3c00479.
 

Other publications of authors with the same name

Low Energy, Highly-Associative Cache Design for Embedded Processors., and . ICCD, page 332-335. IEEE Computer Society, (2004)Low Energy Associative Data Caches for Embedded Systems., , and . Embedded Software for SoC, Kluwer / Springer, (2003)Compiler-Directed Cache Line Size Adaptivity., , , , and . Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 183-187. Springer, (2000)On the Determination of Inlining Vectors for Program Optimization., , , , , and . CC, volume 7791 of Lecture Notes in Computer Science, page 164-183. Springer, (2013)A software coherence scheme with the assistance of directories., and . ICS, page 284-294. ACM, (1991)Compiler-Directed Cache Assist Adaptivity., , , , and . ISHPC, volume 1940 of Lecture Notes in Computer Science, page 88-104. Springer, (2000)Just in Time Load Balancing., , and . LCPC, volume 7760 of Lecture Notes in Computer Science, page 1-16. Springer, (2012)Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache., , , and . IEEE Trans. Computers, 54 (2): 185-197 (2005)MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits., , , , , and . IEEE Trans. VLSI Syst., 19 (12): 2303-2316 (2011)An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors., and . International Journal of Parallel Programming, 27 (1): 35-70 (1999)