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A centralized cache miss driven technique to improve processor power dissipation.

, , , and . ICSAMOS, page 195-202. IEEE, (2008)

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Error-Aware Design., , , , and . DSD, page 8-15. IEEE Computer Society, (2007)Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency., , , and . DAC, page 68-71. ACM, (2008)A centralized cache miss driven technique to improve processor power dissipation., , , and . ICSAMOS, page 195-202. IEEE, (2008)Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors., , , and . LCTES, page 71-78. ACM, (2008)A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment., , , and . IEEE Trans. VLSI Syst., 17 (6): 827-837 (2009)Limits on voltage scaling for caches utilizing fault tolerant techniques., , , and . ICCD, page 488-495. IEEE, (2007)Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices., , and . ICSAMOS, page 124-131. IEEE, (2008)Solutions to a Complete Web Service Discovery and Composition., and . CEC/EEE, page 73. IEEE Computer Society, (2006)ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits., , and . ICCD, page 699-706. IEEE Computer Society, (2008)Multiple sleep mode leakage control for cache peripheral circuits in embedded processors., , and . CASES, page 197-206. ACM, (2008)