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Disambiguation of "Golshan, Shahin"

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Hot peripheral thermal management to mitigate cache temperature variation.

, , , , and . ISQED, page 755-763. IEEE, (2012)

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Shahin Rafiee Taghanaki University of Stuttgart

 

Other publications of authors with the same name

Process variation aware system-level load assignment for total energy minimization using stochastic ordering., , and . ISQED, page 566-571. IEEE, (2011)Hot peripheral thermal management to mitigate cache temperature variation., , , , and . ISQED, page 755-763. IEEE, (2012)SEU-aware resource binding for modular redundancy based designs on FPGAs., and . DATE, page 1124-1129. IEEE, (2009)MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits., , , , , and . IEEE Trans. VLSI Syst., 19 (12): 2303-2316 (2011)SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (6): 829-840 (2011)Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations., , , , , and . CODES+ISSS, page 257-266. ACM, (2011)Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems., , , , , and . ISLPED, page 49-54. ACM, (2010)On leakage power optimization in clock tree networks for ASICs and general-purpose processors., , , , and . SUSCOM, 1 (1): 75-87 (2011)Single-Event-Upset (SEU) Awareness in FPGA Routing., and . DAC, page 330-333. IEEE, (2007)Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks., , , , and . ISQED, page 499-507. IEEE, (2010)