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Power-sensitive multithreaded architecture., , and . ICCD, page 17-24. IEEE Computer Society, (2012)Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors., , and . IPDPS, IEEE, (2006)2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar., and . IEEE Micro, 34 (6): 95-97 (2014)Architecture-Level Power Optimization - What Are the Limits?, and . J. Instruction-Level Parallelism, (2005)Multithreaded Execution Architecture and Compilation., and . HPCA, page 321. IEEE Computer Society, (1999)Accelerating and Adapting Precomputation Threads for Effcient Prefetching., , and . HPCA, page 85-95. IEEE Computer Society, (2007)Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling., , and . ISCA, page 408-419. IEEE Computer Society, (2005)Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06)., , and . SIGARCH Computer Architecture News, 35 (1): 2 (2007)Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08)., , and . SIGARCH Computer Architecture News, 37 (2): 1 (2009)Platform-Agnostic Learning-Based Scheduling., , and . SAMOS, volume 11733 of Lecture Notes in Computer Science, page 142-154. Springer, (2019)