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Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance

, , , and . CoRR, (2007)

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Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS., , , , and . J. Solid-State Circuits, 43 (11): 2422-2433 (2008)Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies., , , , , , , , , and 5 other author(s). ISSCC, page 528-529. IEEE, (2008)A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 44 (12): 3486-3498 (2009)CMOS low-power transceivers for 60GHz multi Gbit/s communications., , , , , , , , , and 7 other author(s). CICC, page 1-8. IEEE, (2013)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance., , , and . DATE, page 270-275. IEEE Computer Society, (2005)A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 408-409. IEEE, (2009)A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS., , , , , , , and . J. Solid-State Circuits, 53 (7): 2001-2011 (2018)A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication., , , , , , , , , and 4 other author(s). ISSCC, page 236-237. IEEE, (2013)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance, , , and . CoRR, (2007)A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s., , , , , , , , , and 2 other author(s). ISSCC, page 268-270. IEEE, (2012)