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Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.

P. Wambacq, A. Mercha, K. Scheir, B. Verbruggen, J. Borremans, V. Heyn, S. Thijs, D. Linten, G. der Plas, B. Parvais, M. Dehan, S. Decoutere, C. Soens, N. Collaert, and M. Jurczak. ISSCC, page 528-529. IEEE, (2008)

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Dr. -Ing. Reinhold Bertrand University of Stuttgart

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A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS.V. Szortyka, Q. Shi, K. Raczkowski, B. Parvais, M. Kuijk, and P. Wambacq. J. Solid-State Circuits, 50 (9): 2025-2036 (2015)A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication.V. Vidojkovic, V. Szortyka, K. Khalaf, G. Mangraviti, S. Brebels, W. Thillo, K. Vaesen, B. Parvais, V. Issakov, M. Libois and 4 other author(s). ISSCC, page 236-237. IEEE, (2013)The Potential of FinFETs for Analog and RF Circuit Applications.P. Wambacq, B. Verbruggen, K. Scheir, J. Borremans, M. Dehan, D. Linten, V. Heyn, G. der Plas, A. Mercha, B. Parvais and 5 other author(s). IEEE Trans. on Circuits and Systems, 54-I (11): 2541-2551 (2007)Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET.D. Ponton, P. Palestri, D. Esseni, L. Selmi, M. Tiebout, B. Parvais, and G. Knoblinger. ISCAS, page 2701-2704. IEEE, (2008)FinFET technology for analog and RF circuits.B. Parvais, V. Subramanian, A. Mercha, M. Dehan, P. Wambacq, W. Sansen, G. Groeseneken, and S. Decoutere. ICECS, page 182-185. IEEE, (2007)Modeling FinFET metal gate stack resistance for 14nm node and beyond.K. Miyaguchi, B. Parvais, L. Ragnarsson, P. Wambacq, P. Raghavan, A. Mercha, A. Mocuta, D. Verkest, and A. Thean. ICICDT, page 1-4. IEEE, (2015)An Accurate Scalable Compact Model for the Substrate Resistance of RF MOSFETs.B. Parvais, S. Hu, M. Dehan, A. Mercha, and S. Decoutere. CICC, page 503-506. IEEE, (2007)Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations.M. Simicic, P. Weckx, B. Parvais, P. Roussel, B. Kaczer, and G. Gielen. IEEE Trans. VLSI Syst., 27 (3): 601-610 (2019)Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.P. Wambacq, A. Mercha, K. Scheir, B. Verbruggen, J. Borremans, V. Heyn, S. Thijs, D. Linten, G. der Plas, B. Parvais and 5 other author(s). ISSCC, page 528-529. IEEE, (2008)Design Technology co-optimization for N10.J. Ryckaert, P. Raghavan, R. Baert, M. Bardon, M. Dusa, A. Mallik, S. Sakhare, B. Vandewalle, P. Wambacq, B. Chava and 18 other author(s). CICC, page 1-8. IEEE, (2014)

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Disambiguation of "Parvais, Bertrand"

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Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.

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Dr. -Ing. Reinhold Bertrand University of Stuttgart

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PUMA

Disambiguation of "Parvais, Bertrand"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.

Please choose a person to relate this publication to

Dr. -Ing. Reinhold Bertrand University of Stuttgart

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Disambiguation

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Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.