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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

F. Lv, X. Zheng, F. Zhao, J. Wang, S. Yue, Z. Wang, W. Cao, Y. He, C. Zhang, H. Jiang, and Z. Wang. Microelectronics Journal, (2018)

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NeuADC: Neural Network-Inspired RRAM-Based Synthesizable Analog-to-Digital Conversion with Reconfigurable Quantization Support.W. Cao, X. He, A. Chakrabarti, and X. Zhang. DATE, page 1477-1482. IEEE, (2019)Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals.W. Cao, Y. Zhao, A. Boloor, Y. Han, X. Zhang, and L. Jiang. CoRR, (2022)Low-Noise Biopotential Recording Circuit with Correlated Timeshare Sampling.H. Li, and W. Cao. GreenCom/iThings/CPScom, page 1810-1812. IEEE, (2013)A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.F. Lv, X. Zheng, F. Zhao, J. Wang, S. Yue, Z. Wang, W. Cao, Y. He, C. Zhang, H. Jiang and 1 other author(s). Microelectronics Journal, (2018)Influence of Surface Roughness on the Pump Performance Based on Computational Fluid Dynamics.X. He, W. Jiao, C. Wang, and W. Cao. IEEE Access, (2019)Virtual Programming Lab for Online Distance Learning.J. Cao, A. Chan, W. Cao, and C. Yeung. ICWL, volume 2436 of Lecture Notes in Computer Science, page 216-227. Springer, (2002)Ultra-low-power Neural Recording Microsystem for Implantable Brain Machine Interface.W. Cao, and H. Li. GreenCom/iThings/CPScom, page 1050-1053. IEEE, (2013)Ciarlet-Raviart mixed finite element approximation for an optimal control problem governed by the first bi-harmonic equation.W. Cao, and D. Yang. J. Computational Applied Mathematics, 233 (2): 372-388 (2009)Adaptive optimal control approximation for solving a fourth-order elliptic variational inequality.W. Cao, and D. Yang. Computers & Mathematics with Applications, 66 (12): 2517-2531 (2014)A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology.N. Zhou, L. Wu, Z. Wang, X. Zheng, W. Cao, C. Zhang, F. Li, and Z. Wang. NEWCAS, page 1-4. IEEE, (2016)

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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.