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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

F. Lv, X. Zheng, F. Zhao, J. Wang, S. Yue, Z. Wang, W. Cao, Y. He, C. Zhang, H. Jiang, and Z. Wang. Microelectronics Journal, (2018)

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A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.X. Zheng, C. Zhang, F. Lv, F. Zhao, S. Yuan, S. Yue, Z. Wang, F. Li, Z. Wang, and H. Jiang. J. Solid-State Circuits, 52 (11): 2963-2978 (2017)Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network.Y. Wang, J. Zhang, Q. Wang, F. Lv, and K. Chen. CWSN, volume 501 of Communications in Computer and Information Science, page 52-58. Springer, (2014)A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.F. Lv, X. Zheng, Z. Wang, J. Wang, and F. Li. ASICON, page 1-4. IEEE, (2015)A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS.X. Zheng, C. Zhang, F. Lv, F. Zhao, S. Yue, Z. Wang, F. Li, H. Jiang, and Z. Wang. CICC, page 1-4. IEEE, (2017)A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.F. Lv, X. Zheng, F. Zhao, J. Wang, S. Yue, Z. Wang, W. Cao, Y. He, C. Zhang, H. Jiang and 1 other author(s). Microelectronics Journal, (2018)A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.X. Zheng, C. Zhang, F. Lv, F. Zhao, S. Yue, Z. Wang, F. Li, and Z. Wang. ESSCIRC, page 305-308. IEEE, (2016)A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.X. Zheng, F. Lv, F. Zhao, S. Yue, C. Zhang, Z. Wang, F. Li, H. Jiang, and Z. Wang. CICC, page 1-4. IEEE, (2017)A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.H. Ding, X. Zheng, D. Wu, L. Zhou, J. Wu, F. Lv, J. Wang, and X. Liu. ESSCIRC, page 195-198. IEEE, (2019)

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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.