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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

F. Lv, X. Zheng, F. Zhao, J. Wang, S. Yue, Z. Wang, W. Cao, Y. He, C. Zhang, H. Jiang, and Z. Wang. Microelectronics Journal, (2018)

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Zheng Li University of Stuttgart

Haoyu Zheng University of Stuttgart

Jianshu Zheng University of Stuttgart

Other publications of authors with the same name

A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS.S. Hu, C. Jia, K. Huang, C. Zhang, X. Zheng, and Z. Wang. ISCAS, page 309-312. IEEE, (2012)A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS.W. Cao, Z. Wang, D. Li, X. Zheng, K. Huang, S. Yuan, F. Li, and Z. Wang. NEWCAS, page 1-4. IEEE, (2015)A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS.S. Yuan, L. Wu, Z. Wang, X. Zheng, P. Wang, W. Jia, C. Zhang, and Z. Wang. ESSCIRC, page 144-147. IEEE, (2015)A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology.K. Huang, Z. Wang, X. Zheng, C. Zhang, and Z. Wang. CICC, page 1-4. IEEE, (2014)A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS.K. Yu, X. Zheng, K. Huang, M. Xuan, Z. Wang, C. Zhang, and Z. Wang. VLSI-DAT, page 1-4. IEEE, (2013)A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.X. Zheng, C. Zhang, F. Lv, F. Zhao, S. Yuan, S. Yue, Z. Wang, F. Li, Z. Wang, and H. Jiang. J. Solid-State Circuits, 52 (11): 2963-2978 (2017)A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS.H. Liu, D. Wu, L. Zhou, Y. Huang, J. Luan, X. Guo, D. Wang, X. Zheng, J. Wu, and X. Liu. IEICE Electronic Express, 16 (3): 20181079 (2019)A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology.S. Yuan, Z. Wang, X. Zheng, K. Huang, L. Wu, and Z. Wang. ASICON, page 1-4. IEEE, (2013)A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology.K. Huang, D. Luo, Z. Wang, X. Zheng, F. Li, C. Zhang, and Z. Wang. CICC, page 1-4. IEEE, (2015)A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.F. Lv, X. Zheng, F. Zhao, J. Wang, S. Yue, Z. Wang, W. Cao, Y. He, C. Zhang, H. Jiang and 1 other author(s). Microelectronics Journal, (2018)

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Disambiguation of "Zheng, Xuqiang"

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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

Please choose a person to relate this publication to

Zheng Li University of Stuttgart

Haoyu Zheng University of Stuttgart

Jianshu Zheng University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Zheng, Xuqiang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.

Please choose a person to relate this publication to

Zheng Li University of Stuttgart

Haoyu Zheng University of Stuttgart

Jianshu Zheng University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Chicago
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A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.