%0 Journal Article %1 journals/mj/LvZZWYWCHZJW18 %A Lv, Fangxu %A Zheng, Xuqiang %A Zhao, Feng %A Wang, Jianye %A Yue, Shigang %A Wang, Ziqiang %A Cao, Weidong %A He, Yajun %A Zhang, Chun %A Jiang, Hanjun %A Wang, Zhihua %D 2018 %J Microelectronics Journal %K dblp %P 36-45 %T A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications. %U http://dblp.uni-trier.de/db/journals/mj/mj82.html#LvZZWYWCHZJW18 %V 82

@article{journals/mj/LvZZWYWCHZJW18, added-at = {2018-12-19T00:00:00.000+0100}, author = {Lv, Fangxu and Zheng, Xuqiang and Zhao, Feng and Wang, Jianye and Yue, Shigang and Wang, Ziqiang and Cao, Weidong and He, Yajun and Zhang, Chun and Jiang, Hanjun and Wang, Zhihua}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/200f503d438b8b620c64552006928cc36/dblp}, ee = {https://doi.org/10.1016/j.mejo.2018.10.007}, interhash = {b6963dc02dbd9a463abea22f84f8665c}, intrahash = {00f503d438b8b620c64552006928cc36}, journal = {Microelectronics Journal}, keywords = {dblp}, pages = {36-45}, timestamp = {2019-09-27T08:54:22.000+0200}, title = {A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.}, url = {http://dblp.uni-trier.de/db/journals/mj/mj82.html#LvZZWYWCHZJW18}, volume = 82, year = 2018 }