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Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.

B. Schmidt, D. Ziener, and J. Teich. IPDPS Workshops, page 299-304. IEEE Computer Society, (2014)

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Daniel Marino

Daniel Roth

Other publications of authors with the same name

Symbolic system-level design methodology for multi-mode reconfigurable systems.S. Wildermann, F. Reimann, D. Ziener, and J. Teich. Design Autom. for Emb. Sys., 17 (2): 343-375 (2013)Power Signature Watermarking of IP Cores for FPGAs.D. Ziener, and J. Teich. Signal Processing Systems, 51 (1): 123-136 (2008)Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems.D. Ziener. CoRR, (2018)Partial Reconfiguration on FPGAs in Practice - Tools and Applications.D. Koch, J. Tørresen, C. Beckhoff, D. Ziener, C. Dennl, V. Breuer, J. Teich, M. Feilen, and W. Stechele. ARCS Workshops, volume P-200 of LNI, page 297-319. GI, (2012)FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN).T. Ziermann, A. Butiu, J. Teich, and D. Ziener. ReConFig, page 1-6. IEEE, (2012)Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration.C. Dennl, D. Ziener, and J. Teich. FCCM, page 25-28. IEEE Computer Society, (2013)On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library.C. Dennl, D. Ziener, and J. Teich. FCCM, page 45-52. IEEE Computer Society, (2012)A rapid prototyping system for error-resilient multi-processor systems-on-chip.M. May, N. Wehn, A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, D. Ziener, and J. Teich. DATE, page 375-380. IEEE, (2010)Stress-Aware Module Placement on Reconfigurable Devices.J. Angermeier, D. Ziener, M. Glaß, and J. Teich. FPL, page 277-281. IEEE Computer Society, (2011)A LUT-Based Approximate Adder.A. Becher, J. Echavarria, D. Ziener, S. Wildermann, and J. Teich. FCCM, page 27. IEEE Computer Society, (2016)

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Disambiguation of "Ziener, Daniel"

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Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.

Please choose a person to relate this publication to

Daniel Marino

Daniel Roth

Daniel Roth

Daniel Roth

Daniel Roth

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Ziener, Daniel"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.

Please choose a person to relate this publication to

Daniel Marino

Daniel Roth

Daniel Roth

Daniel Roth

Daniel Roth

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.