PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Teich, Jürgen"

Author of the publication

copydeleteadd this publication to your clipboard
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning.

, , , and . CoRR, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

apl. Prof. Dr. Jürgen Pleiss University of Stuttgart

Univ. -Prof. Dr. Jürgen Pafel University of Stuttgart

Dr. rer. nat. Jürgen Steinwandel University of Stuttgart

Hon. -Prof. Dr. Jürgen Hammer University of Stuttgart

Hon. -Prof. Dr. Jürgen Blum University of Stuttgart

 

Other publications of authors with the same name

Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays., , and . J. Low Power Electronics, 7 (1): 29-40 (2011)Domain-specific augmentations for High-Level Synthesis., , , , , and . ASAP, page 173-177. IEEE Computer Society, (2014)Acceleration of Multiresolution Imaging Algorithms: A Comparative Study., , , , and . ASAP, page 211-214. IEEE Computer Society, (2009)A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing., , , , and . ASAP, page 331-340. IEEE Computer Society, (2006)Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter., , , and . ASAP, page 299-308. IEEE Computer Society, (2000)Temporal task clustering for online placement on reconfigurable hardware., , and . FPT, page 359-362. IEEE, (2003)From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures.. FPT, page 11-12. IEEE Computer Society, (2009)An FPGA implementation of a threat-based strategy for Connect6., , , , , and . FPT, page 1-4. IEEE, (2011)A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template., , , and . ReCoSoC, page 31-37. Univ. Montpellier II, (2006)Automatic generation of system-level virtual prototypes from streaming application models., , , and . International Symposium on Rapid System Prototyping, page 128-134. IEEE, (2011)