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Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter.

, , , and . ASAP, page 299-308. IEEE Computer Society, (2000)

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Reconfigurable Implementation of Elliptic Curve Crypto Algorithms., , , , and . IPDPS, IEEE Computer Society, (2002)A High Performance VLIW Processor for Finite Field Arithmetic., , , , and . IPDPS, page 189. IEEE Computer Society, (2003)WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach., , , , , , , , , and 10 other author(s). DATE, page 286-289. IEEE, (2017)Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms., and . The Journal of Supercomputing, 26 (2): 149-165 (2003)FPGA designs of parallel high performance GF(2233) multipliers., , , , and . ISCAS (2), page 268-271. IEEE, (2003)Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach., , , , , , , , , and 3 other author(s). ARC, volume 10824 of Lecture Notes in Computer Science, page 700-711. Springer, (2018)Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter., , , and . ASAP, page 299-308. IEEE Computer Society, (2000)Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration., , , and . IPDPS, IEEE Computer Society, (2004)A New Approach for On-line Placement on Reconfigurable Devices., , , and . IPDPS, IEEE Computer Society, (2004)Tradeoff analysis of FPGA based elliptic curve cryptography., , , , and . ISCAS (5), page 797-800. IEEE, (2002)