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Disambiguation of "Radhakrishnan, Swarnalatha"

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Customization of application specific heterogeneous multi-pipeline processors.

, , and . DATE, page 746-751. European Design and Automation Association, Leuven, Belgium, (2006)

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Keerthi Radhakrishnan University of Stuttgart

 

Other publications of authors with the same name

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors., , , and . VLSI Design, page 7-12. IEEE Computer Society, (2013)Loop Unrolling in Multi-pipeline ASIP Design., , and . CoRR, (2014)Application specific forwarding network and instruction encoding for multi-pipe ASIPs., , , and . CODES+ISSS, page 241-246. ACM, (2006)HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors., , , and . IET Computers & Digital Techniques, 3 (1): 94-108 (2009)CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors., , , , , , , and . DATE, page 707-712. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Customization of application specific heterogeneous multi-pipeline processors., , and . DATE, page 746-751. European Design and Automation Association, Leuven, Belgium, (2006)Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study., , and . CoRR, (2014)Dual-pipeline heterogeneous ASIP design., , and . CODES+ISSS, page 12-17. ACM, (2004)DRMA: dynamically reconfigurable MPSoC architecture., , , , , , and . ACM Great Lakes Symposium on VLSI, page 239-244. ACM, (2013)Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (12): 1991-2003 (2015)