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Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study.

, , and . CoRR, (2014)

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RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors., , , and . DIPES/BICC, volume 329 of IFIP Advances in Information and Communication Technology, page 137-144. Springer, (2010)Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion., , and . ASP-DAC, page 819-824. IEEE, (2012)DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks., , and . ASP-DAC, page 620-625. IEEE, (2013)A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES., , , and . ISVLSI, page 76-83. IEEE Computer Socity, (2013)MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping., , and . VLSI Design, page 1-6. IEEE Computer Society, (2013)A smart random code injection to mask power analysis based side channel attacks., , and . CODES+ISSS, page 51-56. ACM, (2007)DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs., , , , and . CODES+ISSS, page 151-160. ACM, (2012)RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks., , and . DAC, page 489-492. IEEE, (2007)ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip., , , , , , , and . ISCAS, page 413-416. IEEE, (2015)CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study., , and . ISCAS, page 253-256. IEEE, (2012)