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ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.

J. Ambrose, N. Higgins, M. Chakravarthy, S. Gargg, T. Li, D. Murphy, A. Ignjatovic, and S. Parameswaran. ISCAS, page 413-416. IEEE, (2015)

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Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks.J. Ambrose, R. Ragel, S. Parameswaran, and A. Ignjatovic. IET Computers & Digital Techniques, 5 (1): 1-15 (2011)A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider.I. Lu, N. Weste, and S. Parameswaran. IEEE Trans. on Circuits and Systems, 54-II (4): 323-327 (2007)Guest editorial for special issue on embedded system security.T. Wolf, and S. Parameswaran. Design Autom. for Emb. Sys., 12 (3): 171-172 (2008)Specification and Design of Multi-Million Gate SOCs.R. Chandra, P. Panda, J. Henkel, S. Parameswaran, and L. Ramachandran. VLSI Design, page 18-19. IEEE Computer Society, (2003)Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.S. Min, J. Peddersen, and S. Parameswaran. VLSI Design, page 141-146. IEEE Computer Society, (2011)Improved Architectures for Range Encoding in Packet Classification System.X. He, J. Peddersen, and S. Parameswaran. NCA, page 10-19. IEEE Computer Society, (2010)Advanced modes in AES: Are they safe from power analysis based side channel attacks?D. Jayasinghe, R. Ragel, J. Ambrose, A. Ignjatovic, and S. Parameswaran. ICCD, page 173-180. IEEE Computer Society, (2014)The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band.I. Lu, N. Weste, and S. Parameswaran. WCNC, page 776-781. IEEE, (2005)Editorial Introduction of New Editor-in-Chief and Associate Editors.S. Parameswaran. Embedded Systems Letters, 8 (1): 1 (2016)Low-Impact Processor for Dynamic Runtime Power Management.J. Peddersen, and S. Parameswaran. IEEE Design & Test of Computers, 25 (1): 52-62 (2008)

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Disambiguation of "Parameswaran, Sri"

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ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.

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Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Parameswaran, Sri"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.

Please choose a person to relate this publication to

Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Disambiguation

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ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip.