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Disambiguation of "Panda, Preeti Ranjan"

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Specification and Design of Multi-Million Gate SOCs.

, , , , and . VLSI Design, page 18-19. IEEE Computer Society, (2003)

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Sidharth Ranjan University of Stuttgart

Karthik Pandaram University of Stuttgart

 

Other publications of authors with the same name

Augmenting Loop Tiling with Data Alignment for Improved Cache Performance., , , and . IEEE Trans. Computers, 48 (2): 142-149 (1999)Memory Organization for Improved Data Cache Performance in Embedded Processors., , and . ISSS, page 90-95. ACM / IEEE Computer Society, (1996)The impact of loop unrolling on controller delay in high level synthesis., , and . DATE, page 391-396. EDA Consortium, San Jose, CA, USA, (2007)Space sensitive cache dumping for post-silicon validation., , and . DATE, page 497-502. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Guest Editorial: Special Issue on VLSI Design and Embedded Systems., and . International Journal of Parallel Programming, 38 (3-4): 183-184 (2010)Energy optimization in Android applications through wakelock placement., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Memory allocation and mapping in high-level synthesis - an integrated approach., , and . IEEE Trans. VLSI Syst., 11 (5): 928-938 (2003)Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD., , , , and . ACM Trans. Embedded Comput. Syst., 15 (1): 18:1-18:23 (2016)Memory data organization for improved cache performance in embedded processor applications., , and . ACM Trans. Design Autom. Electr. Syst., 2 (4): 384-409 (1997)A SysML Profile for Development and Early Validation of TLM 2.0 Models., , and . ECMFA, volume 6698 of Lecture Notes in Computer Science, page 299-311. Springer, (2011)