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O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction., , , , , and . ICICDT, page 1-4. IEEE, (2012)Layout Decomposition and Legalization for Double-Patterning Technology., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (2): 202-215 (2013)A framework for early and systematic evaluation of design rules., and . ICCAD, page 615-622. ACM, (2009)Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model., and . DFT, page 59-67. IEEE Computer Society, (2007)Role of design in multiple patterning: technology development, design enablement and process control., and . DATE, page 314-319. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Pattern-restricted design at 10nm and beyond., , and . ICCD, page 308-310. IEEE Computer Society, (2014)DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (9): 1379-1392 (2012)A framework for double patterning-enabled design., , , , , and . ICCAD, page 14-20. IEEE Computer Society, (2011)A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects., and . J. Electronic Testing, 25 (1): 67-77 (2009)Electrical Modeling of Lithographic Imperfections., , and . VLSI Design, page 423-428. IEEE Computer Society, (2010)