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From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms.

, , , and . DATE, page 186-190. IEEE Computer Society, (1998)

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A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication., , , and . DSD, page 63-70. IEEE Computer Society, (2011)Dynamic quadrant partitioning adaptive routing algorithm for irregular reduced vertical link density topology 3-Dimensional Network-on-Chips., , and . HPCS, page 516-522. IEEE, (2014)Fast and optimized task allocation method for low vertical link density 3-dimensional networks-on-chip based many core systems., , and . DATE, page 1777-1782. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems., , , and . NORCHIP, page 1-4. IEEE, (2012)Reconfigurable platforms for ubiquitous computing., , , , , , , and . Conf. Computing Frontiers, page 377-389. ACM, (2004)A modular 6LoWPAN-based wireless sensor body area network for health-monitoring applications., , , , , , , , , and . APSIPA, page 1-4. IEEE, (2014)Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip., , and . Microprocessors and Microsystems - Embedded Hardware Design, 35 (3): 343-358 (2011)Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method., , and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (6): 449-461 (2012)Hardware Based Rapid Prototyping., , and . Wiley Encyclopedia of Computer Science and Engineering, John Wiley & Sons, Inc., (2008)A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method., , and . ReCoSoC, page 1-8. IEEE, (2014)