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A multi-path high speed Viterbi decoder., , , and . ICECS, page 1160-1163. IEEE, (2003)Dynamic power optimization of the trace-back process for the Viterbi algorithm., , , , , , and . ISCAS (2), page 721-724. IEEE, (2004)A linear model for high-level delay estimation in VDSM on-chip interconnects., , , and . ISCAS (2), page 1078-1081. IEEE, (2005)An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders., , , , , , and . VLSI-SOC, page 167-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques., , , , , , , , and . SAMOS, volume 3553 of Lecture Notes in Computer Science, page 12-21. Springer, (2005)Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures., , , , , , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 1111-1114. Springer, (2003)An Efficient Fractional-Rate Interpolation Architecture., and . GLOBECOM, page 4554-4558. IEEE, (2007)A Scalable Resampling Architecture., and . GLOBECOM, page 3102-3106. IEEE, (2007)Optimal FFT Architecture Selection for OFDM Receivers on FPGA., and . FPT, page 313-314. IEEE, (2005)The XPP Architecture and Its Co-simulation Within the Simulink Environment., , , , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 761-770. Springer, (2004)