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Heterogeneous Modelling of an Optical Network-on-Chip with SystemC., , , , , and . IEEE International Workshop on Rapid System Prototyping, page 10-16. IEEE Computer Society, (2005)Automated synthesis of current-memory cells., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 19 (4): 413-424 (2000)Reducing transistor count in clocked standard cells with ambipolar double-gate FETs., , , , , and . NANOARCH, page 47-52. IEEE Computer Society, (2010)Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices., , , and . NANOARCH, page 69-74. IEEE Computer Society, (2009)Modeling and simulation of networked low-power embedded systems: a taxonomy., , , , and . EURASIP J. Wireless Comm. and Networking, (2014)Foreword., , , and . VLSI-SoC, page 1. IEEE, (2016)Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques., , and . IEEE Trans. Multi-Scale Computing Systems, 4 (2): 97-98 (2018)Ambipolar independent double gate FET logic., , , and . NANOARCH, page 61-68. ACM, (2012)Low-power design technique with ambipolar double gate devices., , , and . NANOARCH, page 14-21. ACM, (2012)Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques., , , , , and . DAC, page 85:1-85:6. ACM, (2017)