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Disambiguation of "Gaillardon, Pierre-Emmanuel"

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Reducing transistor count in clocked standard cells with ambipolar double-gate FETs.

, , , , , and . NANOARCH, page 47-52. IEEE Computer Society, (2010)

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Pierre Nacke University of Stuttgart

Dr. rer. nat. Pierre Eckold University of Stuttgart

Pierre Kuna University of Stuttgart

 

Other publications of authors with the same name

A high-performance low-power near-Vt RRAM-based FPGA., , and . FPT, page 207-214. IEEE, (2014)Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs., , , and . DATE, page 948-953. IEEE, (2016)Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only)., , , , and . FPGA, page 262. ACM, (2015)Post-P&R Performance and Power Analysis for RRAM-Based FPGAs., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 639-650 (2018)Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop., , , , , , and . ISCAS, page 1-4. IEEE, (2017)On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors., , , , , and . ISVLSI, page 491-496. IEEE Computer Society, (2015)A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors., , , and . VLSI-SoC, page 172-177. IEEE, (2019)Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection., , , and . NANOARCH, page 163-168. IEEE Computer Society/ACM, (2014)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors., , , , , , and . NANOARCH, page 55-60. ACM, (2012)Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains., , , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 131-136. ACM, (2017)