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Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations.

, , , and . Microelectronics Journal, 38 (4-5): 463-473 (2007)

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Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies., , and . IEEE Trans. VLSI Syst., 19 (4): 647-658 (2011)Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology., , , and . ISQED, page 580-585. IEEE Computer Society, (2007)Circuit Level Reliability Analysis of Cu Interconnects., , , and . ISQED, page 238-243. IEEE Computer Society, (2004)STT-Based Non-Volatile Logic-in-Memory Framework., , and . Field-Coupled Nanocomputing, volume 8280 of Lecture Notes in Computer Science, Springer, (2014)BIST to Detect and Characterize Transient and Parametric Failures., , and . IEEE Design & Test of Computers, 27 (5): 50-59 (2010)Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits., , , , , and . Microelectronics Journal, 41 (1): 9-16 (2010)Welcome to ISQED 2013., , , , , , , and . ISQED, IEEE, (2013)System-level comparison of power delivery design for 2D and 3D ICs., , and . 3DIC, page 1-7. IEEE, (2009)Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis, , and . CoRR, (2009)Thermal aware cell-based full-chip electromigration reliability analysis., , and . ACM Great Lakes Symposium on VLSI, page 26-31. ACM, (2005)