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On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits.

, , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (2): 229-241 (2011)

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Prospects for WSI: A Manufacturing Perspective.. IEEE Computer, 25 (4): 58-65 (1992)Statistical Simulation of the IC Manufacturing Process., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 1 (3): 120-131 (1982)Improved Yield Model for Submicron Domain., and . DFT, page 2-10. IEEE Computer Society, (1997)Modeling the Difficulty of Sequential Automatic Test Pattern Generation., and . ICCD, page 261-271. IEEE Computer Society, (1996)Fault Tuples in Diagnosis of Deep-Submicron Circuits., , , , , and . ITC, page 233-241. IEEE Computer Society, (2002)Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells., , and . ITC, page 390-399. IEEE Computer Society, (1984)To DFT or Not to DFT?, , , , and . ITC, page 557-566. IEEE Computer Society, (1997)Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing., , and . IEEE Design & Test of Computers, 10 (2): 13-23 (1993)Improving the Quality of Test Education.. ITC, page 1119. IEEE Computer Society, (1991)Current testing.. ITC, page 257. IEEE Computer Society, (1990)