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Disambiguation of "Pleskacz, Witold A."

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Improved Yield Model for Submicron Domain.

, and . DFT, page 2-10. IEEE Computer Society, (1997)

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A. Laukemann

A. Laukemann

A. Vo{\ss}

A. Afkari

A. Laukemann

 

Other publications of authors with the same name

Improvement of integrated circuit testing reliability by using the defect based approach., and . Microelectronics Reliability, 43 (6): 945-953 (2003)ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model., and . Microprocessors and Microsystems - Embedded Hardware Design, 37 (6-7): 693-700 (2013)MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio., , , , and . DDECS, page 144-147. IEEE Computer Society, (2009)Layout to Logic Defect Analysis for Hierarchical Test Generation., , , , and . DDECS, page 35-40. IEEE Computer Society, (2007)Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology., , , and . DDECS, page 218-221. IEEE, (2016)Design of a Wideband Low Noise Amplifier for a FMCW Synthetic Aperture Radar in 130 nm SiGe BiCMOS Technology., , , and . MIXDES, page 131-135. IEEE, (2018)A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology., , and . DDECS, page 131-134. IEEE Computer Society, (2011)Characterization of CMOS sequential standard cells for defect based voltage testing., and . EWDTS, page 49-54. IEEE Computer Society, (2008)Hierarchical test generation for combinational circuits with real defects coverage., , , , , , and . Microelectronics Reliability, 42 (7): 1141-1149 (2002)Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement., , , , , and . Microelectronics Reliability, 41 (12): 2023-2040 (2001)