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Transforming Binary Code for Low-Power Embedded Processors., and . IEEE Micro, 24 (3): 21-33 (2004)Efficient Construction of Aliasing-Free Compaction Circuitry., and . IEEE Micro, 22 (5): 82-92 (2002)Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions., and . Design Autom. for Emb. Sys., 14 (3): 309-326 (2010)Tracing the best test mix through multi-variate quality tracking., and . VTS, page 1-6. IEEE Computer Society, (2013)Register allocation for simultaneous reduction of energy and peak temperature on registers., , , and . DATE, page 20-25. IEEE, (2011)Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs., , and . DATE, page 865-869. EDA Consortium, San Jose, CA, USA, (2007)Reducing Average and Peak Test Power Through Scan Chain Modification., , and . J. Electronic Testing, 19 (4): 457-467 (2003)Hierarchical Modeling of the VLSI Design Process., , and . IEEE Expert, 6 (2): 56-70 (1991)Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?, and . Asian Test Symposium, page 373-378. IEEE Computer Society, (2001)Accumulation-based concurrent fault detection for linear digital state variable systems., and . Asian Test Symposium, page 484-. IEEE Computer Society, (2000)