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Disambiguation of "Mukhopadhyay, Saibal"

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Information theoretic models for signatures in VLSI power delivery systems.

, and . WESS, page 2:1-2:5. ACM, (2014)

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Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices., , , , , and . IEEE Trans. VLSI Syst., 22 (9): 1909-1919 (2014)A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching., and . IEEE Trans. on Circuits and Systems, 61-I (1): 74-83 (2014)A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric., , , , and . IEEE Trans. on Circuits and Systems, 62-II (6): 593-597 (2015)Instruction-based energy estimation methodology for asymmetric manycore processor simulations., , , and . SimuTools, page 166-171. ICST/ACM, (2012)Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (8): 1222-1234 (2012)Postsilicon Adaptation for Low-Power SRAM under Process Variation., , , , and . IEEE Design & Test of Computers, 27 (6): 26-35 (2010)DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (11): 2360-2370 (2018)Electrothermal analysis of spin-transfer-torque random access memory arrays., , , and . JETC, 9 (2): 15:1-15:17 (2013)Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies., , , and . ISCAS, page 384-387. IEEE, (2008)Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies., , , , and . DATE, page 926-931. IEEE Computer Society, (2005)