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Disambiguation of "Bhunia, Swarup"

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A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric.

, , , , and . IEEE Trans. on Circuits and Systems, 62-II (6): 593-597 (2015)

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Security Through Obscurity: An Approach for Protecting Register Transfer Level Hardware IP., and . HOST, page 96-99. IEEE Computer Society, (2009)MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications., , , , and . IEEE Trans. VLSI Syst., 23 (6): 1005-1016 (2015)A Flexible Architecture for Systematic Implementation of SoC Security Policies., , and . ICCAD, page 536-543. IEEE, (2015)Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar., and . ISQED, page 697-701. IEEE Computer Society, (2008)Sequential hardware Trojan: Side-channel aware design and placement., , , , and . ICCD, page 297-300. IEEE Computer Society, (2011)Secure and Trusted SoC: Challenges and Emerging Solutions., , and . MTV, page 29-34. IEEE Computer Society, (2013)Current based PUF exploiting random variations in SRAM cells., , , and . DATE, page 277-280. IEEE, (2016)Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations., , , and . IEEE Trans. VLSI Syst., 13 (11): 1286-1295 (2005)Exploring Spin Transfer Torque Devices for Unconventional Computing., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 5-16 (2015)A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks., , , and . ISQED, page 358-363. IEEE Computer Society, (2005)