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A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.

, , , and . ISQED, page 358-363. IEEE Computer Society, (2005)

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Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies., , , , and . DATE, page 926-931. IEEE Computer Society, (2005)GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks., , , and . IEEE Trans. Computers, 54 (6): 752-766 (2005)A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology., and . ISLPED, page 159-164. ACM, (2010)A process-tolerant cache architecture for improved yield in nanoscale technologies., , , , and . IEEE Trans. VLSI Syst., 13 (1): 27-38 (2005)Symmetric Laplacians, Quantum Density Matrices and their Von-Neumann Entropy., , and . CoRR, (2017)Speed binning aware design methodology to improve profit under parameter variations., , , , and . ASP-DAC, page 712-717. IEEE, (2006)A Petri Net Based Model for Multipoint Multistream Synchronization in Multimedia Conferencing., , and . SUComS, volume 223 of Communications in Computer and Information Science, page 64-73. Springer, (2011)Quantum Enhanced Classical Sensor Networks., , and . GLOBECOM Workshops, page 1-6. IEEE, (2017)An Ontology Based Framework for Domain Analysis of Interactive System., , and . IC3 (1), volume 94 of Communications in Computer and Information Science, page 391-402. Springer, (2010)Experiments and analysis to characterize logic state retention limitations in 28nm process node., , , , , , , , , and 7 other author(s). VTS, page 1-6. IEEE Computer Society, (2013)