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A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider., , and . IEEE Trans. on Circuits and Systems, 54-II (4): 323-327 (2007)Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks., , , and . IET Computers & Digital Techniques, 5 (1): 1-15 (2011)Improved Architectures for Range Encoding in Packet Classification System., , and . NCA, page 10-19. IEEE Computer Society, (2010)Dynamic encryption key design and management for memory data encryption in embedded systems., , and . ISVLSI, page 70-75. IEEE Computer Socity, (2013)Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm., , , and . DATE, page 920-925. IEEE, (2010)CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors., , , , , , , and . DATE, page 707-712. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs., , and . DATE, page 1-6. European Design and Automation Association, (2014)Code placement in hardware/software co-synthesis to improve performance and reduce cost.. DATE, page 626-632. IEEE Computer Society, (2001)Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors., , and . DATE, page 875-880. IEEE, (2012)Customization of application specific heterogeneous multi-pipeline processors., , and . DATE, page 746-751. European Design and Automation Association, Leuven, Belgium, (2006)