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Superimposed in-circuit debugging for self-healing FPGA overlays., and . LATS, page 1-6. IEEE, (2018)An Integrated on-Silicon Verification Method for FPGA Overlays., , , and . J. Electronic Testing, 35 (2): 173-189 (2019)Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration., and . IPDPS Workshops, page 277-282. IEEE Computer Society, (2016)Test set generation almost for free using a run-time FPGA reconfiguration technique., and . LATS, page 1-6. IEEE Computer Society, (2015)Parameterised FPGA reconfigurations for efficient test set generation., , and . ReConFig, page 1-6. IEEE, (2014)Special Issue: “Approximation at the Edge”, , , , and . ACM transactions on embedded computing systems, 22 (4): 72 (2023)Test Aspects of System Health State Monitoring, , , , and . 24th IEEE Latin American Test Symposium, Piscataway, NJ, IEEE, (2023)SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs., , and . IOLTS, page 5-8. IEEE, (2017)In-Circuit Debugging with Dynamic Reconfiguration of FPGA Interconnects., and . ACM Trans. Reconfigurable Technol. Syst., 13 (1): 5:1-5:29 (2020)Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization, , , , and . 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS), IEEE, (2023)