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Impact of Self-Heating on Negative-Capacitance FinFET : Device-Circuit Interaction

O. Prakash, G. Pahwa, C. Dabhi, Y. Chauhan, and H. Amrouch. IEEE transactions on electron devices, 68 (4): 1420-1424 (2021)
DOI: 10.1109/TED.2021.3059180

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Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.M. Rapp, S. Salamin, H. Amrouch, G. Pahwa, Y. Chauhan, and J. Henkel. DAC, page 41. ACM, (2019)Design Automation for Cryogenic CMOS CircuitsV. Santen, M. Walter, F. Klemme, S. Parihar, G. Pahwa, Y. Chauhan, R. Wille, and H. Amrouch. 2023 60th ACM/IEEE Design Automation Conference (DAC), IEEE, (2023)Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.H. Amrouch, G. Pahwa, A. Gaidhane, J. Henkel, and Y. Chauhan. IEEE Access, (2018)On the Critical Role of Ferroelectric Thickness for Negative Capacitance Transistor OptimizationO. Prakash, A. Gupta, G. Pahwa, Y. Chauhan, and H. Amrouch. 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Piscataway, IEEE, (2021)Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.G. Pahwa, T. Dutta, A. Agarwal, and Y. Chauhan. ESSCIRC, page 49-54. IEEE, (2016)Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETsS. Parihar, S. Thomann, G. Pahwa, Y. Chauhan, and H. Amrouch. IEEE open journal of circuits and systems, (2023)On the Resiliency of NCFET Circuits Against Voltage Over-ScalingG. Paim, G. Zervakis, G. Pahwa, Y. Chauhan, E. Da Costa, S. Bampi, J. Henkel, and H. Amrouch. IEEE transactions on circuits and systems. 1, Regular papers, 68 (4): 1481-1492 (2021)Impact of Self-Heating on Negative-Capacitance FinFET : Device-Circuit InteractionO. Prakash, G. Pahwa, C. Dabhi, Y. Chauhan, and H. Amrouch. IEEE transactions on electron devices, 68 (4): 1420-1424 (2021)NCFET-Aware Voltage Scaling.S. Salamin, M. Rapp, H. Amrouch, G. Pahwa, Y. Chauhan, and J. Henkel. ISLPED, page 1-6. IEEE, (2019)Impact of Interface Traps on Negative Capacitance Transistor : Device and Circuit ReliabilityO. Prakash, A. Gupta, G. Pahwa, J. Henkel, Y. Chauhan, and H. Amrouch. IEEE journal of the Electron Devices Society, (2020)

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Impact of Self-Heating on Negative-Capacitance FinFET : Device-Circuit Interaction

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Impact of Self-Heating on Negative-Capacitance FinFET : Device-Circuit Interaction

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Impact of Self-Heating on Negative-Capacitance FinFET : Device-Circuit Interaction