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Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs., , , and . ICCAD, page 135-142. ACM, (2006)Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow., , , and . SLIP, page 3-8. ACM, (2006)The Stratix™ 10 Highly Pipelined FPGA Architecture., , , , , , , , and . FPGA, page 159-168. ACM, (2016)An OpenCL(TM) Deep Learning Accelerator on Arria 10., , , , and . CoRR, (2017)DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration., , , , , , , , , and 1 other author(s). FPL, page 411-418. IEEE Computer Society, (2018)Harnessing Numerical Flexibility for Deep Learning on FPGAs., , , , , , , , , and 1 other author(s). HEART, page 1:1-1:3. ACM, (2018)Flexibility: FPGAs and CAD in Deep Learning Acceleration., , , , and . ISPD, page 34-41. ACM, (2018)Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow., , , and . IEEE Trans. VLSI Syst., 15 (8): 895-903 (2007)An OpenCL™ Deep Learning Accelerator on Arria 10., , , , and . FPGA, page 55-64. ACM, (2017)Creating High Performance Applications with Intel's FPGA OpenCL™ SDK., , , , and . IWOCL, page 11:1. ACM, (2017)