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Disambiguation of "Capalija, Davor"

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An OpenCL™ Deep Learning Accelerator on Arria 10.

, , , , and . FPGA, page 55-64. ACM, (2017)

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Other publications of authors with the same name

Flexibility: FPGAs and CAD in Deep Learning Acceleration., , , , and . ISPD, page 34-41. ACM, (2018)Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays., and . FPL, page 1-8. IEEE, (2014)Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor., and . IEEE Trans. Parallel Distrib. Syst., 24 (2): 392-405 (2013)An OpenCL™ Deep Learning Accelerator on Arria 10., , , , and . FPGA, page 55-64. ACM, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)., , , , , , , , , and 1 other author(s). FPGA, page 287. ACM, (2018)Creating High Performance Applications with Intel's FPGA OpenCL™ SDK., , , , and . IWOCL, page 11:1. ACM, (2017)Towards Synthesis-Free JIT Compilation to Commodity FPGAs., and . FCCM, page 202-205. IEEE Computer Society, (2011)A high-performance overlay architecture for pipelined execution of data flow graphs., and . FPL, page 1-8. IEEE, (2013)An OpenCL(TM) Deep Learning Accelerator on Arria 10., , , , and . CoRR, (2017)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC., , , , , , , , , and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)