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A Low-Power Processor Architecture Optimized forWireless Devices., , and . ASAP, page 185-190. IEEE Computer Society, (2005)AMULET3i Cache Architecture., and . ASYNC, page 152-161. IEEE Computer Society, (2001)An asynchronous copy-back cache architecture., , and . Microprocessors and Microsystems, 27 (10): 485-500 (2003)Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application., , , , and . IEEE Trans. Biomed. Circuits and Systems, 12 (5): 1018-1026 (2018)DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs., , , and . CoRR, (2015)AMULET1: A Micropipelined ARM., , , , and . COMPCON, page 476-485. IEEE Computer Society, (1994)An Asynchronous Victim Cache., , and . DSD, page 4-11. IEEE Computer Society, (2002)Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA., , , and . DSD, page 607-614. IEEE Computer Society, (2014)The Amulet chips: Architectural development for asynchronous microprocessors., , , and . ICECS, page 343-346. IEEE, (2009)An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults., , , , and . ASYNC, page 9-16. IEEE Computer Society, (2014)