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Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance., , and . ICCD, page 703-710. IEEE Computer Society, (2005)Modeling Spiking Neural Networks on SpiNNaker., , , , , and . Computing in Science and Engineering, 12 (5): 91-97 (2010)The SpiNNaker Project., , , and . Proceedings of the IEEE, 102 (5): 652-665 (2014)SpiNNaker - Programming Model., , , , , , and . IEEE Trans. Computers, 64 (6): 1769-1782 (2015)SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture., , , , , , , , , and 7 other author(s). Parallel Computing, 39 (11): 693-708 (2013)Concurrency-oriented optimization for low-power asynchronous systems., and . ISLPED, page 151-156. IEEE, (1996)Network-on-chip evaluation for a novel neural architecture., , , and . CF, page 216-219. ACM, (2018)The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip., , and . DATE, page 274-279. IEEE Computer Society, (2004)SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network., , , , and . Conf. Computing Frontiers, page 11-20. ACM, (2010)Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems., , , , , , , , and . ISCAS, page 1. IEEE, (2017)