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Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures., , , , , and . IEEE Trans. VLSI Syst., 17 (1): 151-155 (2009)Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes., , , and . FPL, page 106-111. IEEE, (2005)Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture., , and . FPL, page 622-625. IEEE, (2005)Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays., , , and . FPT, page 33-40. IEEE, (2004)Architecture Exploration for a Reconfigurable Architecture Template., , , , and . IEEE Design & Test of Computers, 22 (2): 90-101 (2005)Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling., , , , and . DATE, page 10296-10301. IEEE Computer Society, (2003)DRESC: a retargetable compiler for coarse-grained reconfigurable architectures., , , , and . FPT, page 166-173. IEEE, (2002)Hardware and a Tool Chain for ADRES., , , , , , , , , and 6 other author(s). ARC, volume 3985 of Lecture Notes in Computer Science, page 425-430. Springer, (2006)Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware., , , , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 264-274. Springer, (2001)ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix., , , , and . FPL, volume 2778 of Lecture Notes in Computer Science, page 61-70. Springer, (2003)