Author of the publication

FPGA-Efficient Hybrid LUT/CORDIC Architecture.

, , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 933-937. Springer, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture., , , and . DSD, page 35-42. IEEE Computer Society, (2007)A single chip 200 MHz digital correlation system for laser spectroscopy with 512 correlation channels., , , and . ISCAS (5), page 160-163. IEEE, (1999)Transmission gate delay models for circuit optimization., , and . EURO-DAC, page 558-562. IEEE Computer Society, (1990)Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators., , and . ESM, page 625-629. SCS Europe, (2002)Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 9 (3): 236-247 (1990)FPGA-efficient phase-to-I/Q architecture., , and . SoCC, page 373-376. IEEE, (2004)Opening a M. Sc. in Electrical Engineering for non-traditional Students., , and . iJAC, 5 (2): 15-19 (2012)FPGA-Efficient Hybrid LUT/CORDIC Architecture., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 933-937. Springer, (2004)VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers., , and . DAC, page 573-578. ACM, (2001)