%0 Conference Paper %1 conf/eurodac/EiseleHK90 %A Eisele, Veronika %A Hoppe, Bernhard %A Kiehl, Oliver %B EURO-DAC %D 1990 %E Adshead, Gordon %E Jess, Jochen A. G. %I IEEE Computer Society %K dblp %P 558-562 %T Transmission gate delay models for circuit optimization. %U http://dblp.uni-trier.de/db/conf/eurodac/euro-dac1990.html#EiseleHK90 %@ 0-8186-2024-2

@inproceedings{conf/eurodac/EiseleHK90, added-at = {2015-11-11T00:00:00.000+0100}, author = {Eisele, Veronika and Hoppe, Bernhard and Kiehl, Oliver}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/297e3fb9c273038c268a0ed6398d970d2/dblp}, booktitle = {EURO-DAC}, crossref = {conf/eurodac/1990}, editor = {Adshead, Gordon and Jess, Jochen A. G.}, ee = {http://dl.acm.org/citation.cfm?id=950096}, interhash = {7600bf35b29305b1b4c5d8cd72d9ef3b}, intrahash = {97e3fb9c273038c268a0ed6398d970d2}, isbn = {0-8186-2024-2}, keywords = {dblp}, pages = {558-562}, publisher = {IEEE Computer Society}, timestamp = {2016-02-02T14:57:09.000+0100}, title = {Transmission gate delay models for circuit optimization.}, url = {http://dblp.uni-trier.de/db/conf/eurodac/euro-dac1990.html#EiseleHK90}, year = 1990 }