%0 Journal Article %1 journals/tcad/HoppeNSS90 %A Hoppe, Bernhard %A Neuendorf, Gerd %A Schmitt-Landsiedel, Doris %A Specks, J. Will %D 1990 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 3 %P 236-247 %T Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation. %U http://dblp.uni-trier.de/db/journals/tcad/tcad9.html#HoppeNSS90 %V 9

@article{journals/tcad/HoppeNSS90, added-at = {2016-03-18T00:00:00.000+0100}, author = {Hoppe, Bernhard and Neuendorf, Gerd and Schmitt-Landsiedel, Doris and Specks, J. Will}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2dcbad6c017ac4fb5910a1467915b3d9b/dblp}, ee = {http://dx.doi.org/10.1109/43.46799}, interhash = {2f36a6290eecca00137e88b98cba2eb0}, intrahash = {dcbad6c017ac4fb5910a1467915b3d9b}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 3, pages = {236-247}, timestamp = {2016-03-19T10:32:57.000+0100}, title = {Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad9.html#HoppeNSS90}, volume = 9, year = 1990 }