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Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.

, , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 9 (3): 236-247 (1990)

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Computer-aided design and scaling of deep submicron CMOS., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 12 (9): 1357-1367 (1993)Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 9 (3): 236-247 (1990)