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Disambiguation of "Zergainoh, Nacer-Eddine"

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Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study.

, , and . J. Electronic Testing, 29 (3): 383-400 (2013)

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Interlanguage Communication Synthesis for Heterogeneous Specifications., , , , , , and . Design Autom. for Emb. Sys., 5 (3-4): 223-236 (2000)Eliminating speed penalty in ECC protected memories., , and . DATE, page 1614-1619. IEEE, (2011)A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis., , and . ETS, page 1-2. IEEE, (2014)Variability-aware task mapping strategies for many-cores processor chips., , , and . IOLTS, page 55-60. IEEE Computer Society, (2011)Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation., , and . IEEE Trans. VLSI Syst., 14 (4): 349-360 (2006)A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs., , and . DFT, page 121-126. IEEE Computer Society, (2016)Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study., , and . J. Electronic Testing, 29 (3): 383-400 (2013)SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core., , , and . LATS, page 1-4. IEEE, (2017)Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip., , , , and . Design Autom. for Emb. Sys., 11 (2-3): 167-191 (2007)Generic Architecture Platform for Multiprocessor System-On-Chip Design., , , and . DIPES, volume 189 of IFIP Conference Proceedings, page 53-64. Kluwer, (2000)