%0 Journal Article %1 journals/tvlsi/ZergainohTJ06 %A Zergainoh, Nacer-Eddine %A Tambour, Ludovic %A Jerraya, Ahmed Amine %D 2006 %J IEEE Trans. VLSI Syst. %K dblp %N 4 %P 349-360 %T Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#ZergainohTJ06 %V 14

@article{journals/tvlsi/ZergainohTJ06, added-at = {2016-03-15T00:00:00.000+0100}, author = {Zergainoh, Nacer-Eddine and Tambour, Ludovic and Jerraya, Ahmed Amine}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/204172eced28411b0750537a3fb99929b/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2006.874360}, interhash = {cef4498ac7396b6bacafe12a7c5b42f3}, intrahash = {04172eced28411b0750537a3fb99929b}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 4, pages = {349-360}, timestamp = {2016-03-16T10:32:18.000+0100}, title = {Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#ZergainohTJ06}, volume = 14, year = 2006 }