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Disambiguation of "Reviriego, Pedro"

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Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate.

, , , and . Trans. Emerging Telecommunications Technologies, 23 (3): 227-233 (2012)

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Dr. Elisete Pedrollo University of Stuttgart

 

Other publications of authors with the same name

Soft error detection and correction for FFT based convolution using different block lengths., , , and . IOLTS, page 138-143. IEEE Computer Society, (2009)Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches., , , , , , and . IOLTS, page 1-6. IEEE, (2014)Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes., , , and . IEEE Trans. Computers, 68 (5): 798-803 (2019)Reliability analysis of memories protected with BICS and a per-word parity bit., , and . ACM Trans. Design Autom. Electr. Syst., 15 (2): 18:1-18:15 (2010)Mitigating the effects of large multiple cell upsets (MCUs) in memories., , , , and . ACM Trans. Design Autom. Electr. Syst., 16 (4): 45:1-45:10 (2011)Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network., , , , , , , and . The Journal of Supercomputing, 62 (3): 1284-1304 (2012)A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets., and . Microelectronics Reliability, 49 (7): 707-715 (2009)Mitigation of permanent faults in adaptive equalizers., , and . Microelectronics Reliability, 51 (3): 703-710 (2011)Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs., , and . Microelectronics Reliability, (2016)Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters., , and . IEEE Trans. on Circuits and Systems, 58-II (8): 512-516 (2011)