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ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.

, , and . VLSI Design, page 575-580. IEEE Computer Society, (2006)

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A simple digital architecture for a harmonic-cancelling sine-wave synthesizer., , , , and . ISCAS, page 2113-2116. IEEE, (2014)Low-Impact Processor for Dynamic Runtime Power Management., and . IEEE Design & Test of Computers, 25 (1): 52-62 (2008)A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider., , and . IEEE Trans. on Circuits and Systems, 54-II (4): 323-327 (2007)Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks., , , and . IET Computers & Digital Techniques, 5 (1): 1-15 (2011)Improved Architectures for Range Encoding in Packet Classification System., , and . NCA, page 10-19. IEEE Computer Society, (2010)Specification and Design of Multi-Million Gate SOCs., , , , and . VLSI Design, page 18-19. IEEE Computer Society, (2003)Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction., , and . VLSI Design, page 141-146. IEEE Computer Society, (2011)Dynamic encryption key design and management for memory data encryption in embedded systems., , and . ISVLSI, page 70-75. IEEE Computer Socity, (2013)Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs., , and . DATE, page 1-6. European Design and Automation Association, (2014)Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm., , , and . DATE, page 920-925. IEEE, (2010)