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ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.

, , and . VLSI Design, page 575-580. IEEE Computer Society, (2006)

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Guest editorial for special issue on embedded system security., and . Design Autom. for Emb. Sys., 12 (3): 171-172 (2008)A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider., , and . IEEE Trans. on Circuits and Systems, 54-II (4): 323-327 (2007)Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks., , , and . IET Computers & Digital Techniques, 5 (1): 1-15 (2011)Improved Architectures for Range Encoding in Packet Classification System., , and . NCA, page 10-19. IEEE Computer Society, (2010)Specification and Design of Multi-Million Gate SOCs., , , , and . VLSI Design, page 18-19. IEEE Computer Society, (2003)Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction., , and . VLSI Design, page 141-146. IEEE Computer Society, (2011)Dynamic encryption key design and management for memory data encryption in embedded systems., , and . ISVLSI, page 70-75. IEEE Computer Socity, (2013)Code placement in hardware/software co-synthesis to improve performance and reduce cost.. DATE, page 626-632. IEEE Computer Society, (2001)Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors., , and . DATE, page 875-880. IEEE, (2012)CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors., , , , , , , and . DATE, page 707-712. EDA Consortium San Jose, CA, USA / ACM DL, (2013)