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Joint affine transformation and loop pipelining for mapping nested loop on CGRAs.

S. Yin, D. Liu, L. Liu, S. Wei, and Y. Guo. DATE, page 115-120. ACM, (2015)

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An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications.L. Liu, C. Deng, D. Wang, M. Zhu, S. Yin, P. Cao, and S. Wei. CICC, page 1-4. IEEE, (2013)Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms.S. Yin, P. Ouyang, L. Liu, and S. Wei. DATE, page 1-6. European Design and Automation Association, (2014)Battery aware tasks allocating algorithm for multi-battery operated system.P. Ouyang, S. Yin, L. Liu, and S. Wei. APCCAS, page 875-878. IEEE, (2010)CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache.S. Yin, W. Xu, J. Li, L. Liu, and S. Wei. IEEE Trans. VLSI Syst., 24 (7): 2548-2561 (2016)A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures.L. Liu, C. Wu, C. Deng, S. Yin, Q. Wu, J. Han, and S. Wei. IEEE Trans. VLSI Syst., 23 (11): 2566-2580 (2015)Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.L. Liu, B. Wang, C. Deng, M. Zhu, S. Yin, and S. Wei. IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (12): 3081-3094 (2018)Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.J. Gu, S. Yin, L. Liu, and S. Wei. IEEE Trans. Parallel Distrib. Syst., 29 (9): 2105-2120 (2018)Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints.C. Wu, C. Deng, L. Liu, S. Yin, J. Han, and S. Wei. SCIENCE CHINA Information Sciences, 58 (8): 1-14 (2015)A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching.L. Liu, Q. Wang, W. Zhu, H. Mo, T. Wang, S. Yin, Y. Shi, and S. Wei. IEEE Trans. Circuits Syst. Video Techn., 29 (8): 2467-2481 (2019)Reconfigurable Architecture for Neural Approximation in Multimedia Computing.F. Tu, S. Yin, P. Ouyang, L. Liu, and S. Wei. IEEE Trans. Circuits Syst. Video Techn., 29 (3): 892-906 (2019)

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Joint affine transformation and loop pipelining for mapping nested loop on CGRAs.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Joint affine transformation and loop pipelining for mapping nested loop on CGRAs.

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Joint affine transformation and loop pipelining for mapping nested loop on CGRAs.